The DDR3 memory controller, adhering to the JESD79-3C standard, facilitates seamless communication between processors and DDR3 SDRAM memory devices. It establishes a glueless connection, supporting features like self-refresh mode, prioritized refresh, and customizable parameters such as refresh rate and CAS latency (Very similar to DDR2 SDRAM). Notably, DDR3 SDRAM introduces Dynamic ODT, a function addressing signal reflection by incorporating termination resistance within the DDR3 SDRAM, enhancing signal integrity in high-speed memory interfaces.

Interfacing DDR3 SDRAM with a DDR3 controller involves selecting a compatible MPU/FPGA/Controller, understanding DDR3 specifications, and interfacing the DDR3 SDRAM according to its datasheet. Ensure proper clocking, address and command signal connections, and data bus routing with attention to signal integrity. Provide stable power and ground, implement termination and impedance matching, and consider calibration and training algorithms supported by the DDR3 controller. Rigorously test the interface using simulation tools and hardware debuggers, and document the design details, referring to the datasheets of the DDR3 controller and SDRAM for specific guidelines.

Few new signles like ZQ Calibration and Reset Pin Functionality is newly added. ZQ calibration is intended to control the on-die termination (ODT) values and output drivers (RTT and RON respectively) of the SDRAM.  This reset pin is designed to allow the user to clear all data (information) stored the DDR3 SDRAM.

DDR3 SDRAM Memory Signal Definition

Below are the DDR3 SDRAM (64-Bits) signals along with Direction and Active stage informationms. The number of address and data pins can vary based on the memory size and organization. Always refer to the datasheet of the specific DDR3 SDRAM device for accurate and detailed information.

Pins	Active Level	Description
DDRD [63:0]	NA	Bidirectional data bus. Input for data reads and output for data writes.
DDRCB [7:0]	NA	Bidirectional data bus (check bits) for ECC byte lane. Input for data reads and output for data writes.
DDRA [15:0]	NA	External address output.
DDRCE0	Low	Active-low chip enable for memory space CE0. DDRCE0z is used to enable the DDR3 SDRAM memory device during external memory accesses.
DDRCE1	Low	Active-low chip enable for memory space CE1 DDRCE1z is used to enable the DDR3 SDRAM memory device during external memory accesses.
DDRDQM [8:0]	High	Active-high output data mask.
DDR3CLKOUTP [1:0]/	NA	Differential clock outputs.
DDR3CLKOUTN [1:0]	NA	Differential clock outputs.
DDRCKE [1:0]	High	Clock enable (used for self-refresh mode).
DDRCAS	Low	Active-low column address strobe.
DDRRAS	Low	Active-low row address strobe.
DDRWE	Low	Active-low write enable.
DDRDQSP [8:0]/	NA	Differential data strobe bidirectional signals.
DDRDQSN [8:0]	NA	Differential data strobe bidirectional signals.
DDRODT [1:0]	High	On-die termination signal(s) to external DDR3 SDRAM
DDRBA [2:0]	NA	Bank-address control outputs
VREFSSTTL	NA	DDR3 Memory Controller reference voltage. This voltage must be supplied externally.
DDRSLRATE [1:0]	NA	Slew Rate Control

DDR3 SDRAM Functional Description

The DDR3/DDR3L Synchronous Dynamic Random-Access Memory (SDRAM) employs a double data rate architecture to achieve high-speed operation, utilizing an 8n-prefetch design that transfers two data words per clock cycle at the I/O pins. A read or write operation involves a single 8n-bit-wide, four-clock-cycle data transfer internally and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Differential data strobe (DQS, DQS#) is transmitted externally with data for use in data capture, and DQS is center-aligned with data for WRITE operations. Read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes.

Operated by a differential clock (CK and CK#), DDR3 SDRAM registers control, command, and address signals at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses are burst-oriented, starting with an ACTIVATE command, followed by a READ or WRITE command. The registered address bits with ACTIVATE select the bank and row, while those with READ or WRITE determine the bank and starting column for the burst access.

The device operates with READ and WRITE BL8 and BC4. An auto precharge function may be enabled for a self-timed row precharge at the end of the burst access. The pipelined, multibank architecture allows for concurrent operation, enhancing bandwidth by hiding row precharge and activation time. Additionally, the DDR3 SDRAM features a self-refresh mode and a power-saving, power-down mode for efficient power management.

DDR3 SDRAM Memory Interface

An example of interfacing Connecting Two 16 MB x 16 x 8 Banks (Total Memory Size 4Gb) Devices is shown in below picture.

An example of interfacing Connecting Two 16 MB x 8 x 8 Banks (Total Memory Size 2Gb) Devices is shown in below picture.

An example of interfacing Connecting one 8MB x 16 x 8 Banks (Total Memory Size 1 Gb) Devices is shown in below picture.

DDR3 SDRAM Signal Descriptions

DDR3 SDRAM devices use several signals for control and data transfer. Few of the key DDR3 SDRAM is as below:-

CK, nCK(System Clock) I/P: DDR3 SDRAM differential Clock input, samples data on rising/falling edge. This is the primary clock signal from the DDR3 SDRAM controller to memory that controls the timing and synchronizes the operation of all DDR3 SDRAM operations. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE I/P: Clock enable, DDR3 SDRAM Clock Enable. CKE signal, when registered HIGH, activates the clocking circuitry, and when registered LOW, deactivates it. CKE LOW enables precharge power-down, SELF REFRESH (all banks idle), or ACTIVATE power-down (row active in any bank). CKE is synchronous for power-down entry/exit, output disable, and self-refresh entry, and asynchronous for self-refresh exit. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_15 input, detecting LVCMOS LOW after VDD during the first power-up. VREF stability is crucial for proper CKE receiver operation and SELF REFRESH, needing maintenance after becoming stable during the power-on sequence.

CS (Chip Select) I/P: The Chip Select signal is used to enable (sampled LOW) or disable (sampled HIGH) the SDRAM device. When active (typically low), command input is valid & DDR3 SDRAM responds to commands and data. When the CS signal is high, all commands are ignored but the operation continues. CS# is referenced to VREFCA.

DQ [63:0] I/O: The DQ input/output Data Bus signals for reading from and writing to the memory are synchronized with the positive and negative edges of CLK. The IOs are byte-makeable during Reads and Writes

A(n:0)- A14, A13, A12/BC#,A10/AP, A [9:0] I/P: DDR3 Address Bus.  DDR3 memory addressing and command structure involves specific address lines for different commands. During an ACTIVATE command, row address lines are used to select a specific row in the memory array. For READ and WRITE commands, the column address is utilized to pinpoint a location within the previously activated row, with the auto precharge bit (A10) determining whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). The address inputs during a LOAD MODE command provide the op-code referenced to VREFCA. Additionally, A12, when enabled, is sampled during READ and WRITE commands to decide between burst chop options(on-the-fly), with A12 HIGH corresponding to BL8 or no burst chop, and A12 LOW indicating BC4. These specifications are crucial for ensuring proper DDR3 memory operation.

LDM, UDM, DM (Data Mask) I/P: In DDR3 memory, the DM (Data Mask) signal serves as an input mask for write data. When DM is sampled HIGH along with input data during a WRITE access, the corresponding data is masked. The sampling of DM occurs on both edges of DQS (Data Strobe). While DM balls are input-only, their loading is designed to match that of DQ (Data) and DQS balls, ensuring consistent performance. Additionally, the terms LDM and UDM refer to DM signals for the lower byte (DQ[7:0]) and upper byte (DQ[15:8]), respectively.

ODT (On-die termination), I/P: In DDR3 SDRAM, the ODT (On-Die Termination) signal, when registered HIGH, activates termination resistance internally. This termination is selectively applied to specific balls based on the memory configuration: for x16, it includes DQ[16:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#; for x8, it involves DQ[7:0], DQS, DQS#, RDQS, RDQS#, and DM; and for x4, it applies to DQ[3:0], DQS, DQS#, and DM. It’s important to note that the ODT input can be ignored if disabled via the LOAD MODE command.

Data strobe signal (DQS, DQS#), I/O: Data Strobe (DQS) serves different roles based on the operation. For read operations, it is an output for read data, and for write operations, it is an input with the write data. In source synchronous operation, the DQS is edge-aligned with the read data and center-aligned with the write data. It’s important to note that DQS# is utilized only when the differential data strobe mode is enabled through the LOAD MODE command.

CAS (Column Address Strobe) I/P: The Column Address Strobe CAS# is an active low command signal issued by the DDR3 SDRAM controller to DDR3 SDRAM Memory. It is issued within conjunction with the RAS# and signals and is latched at the positive edges of CLK. Different signal levels of RAS, CAS, WE and CS, DDR3 SDRAM controller issues different types of commands to DDR3 SDRAM Memory to perform different operations and are referenced to VREFCA.

RAS (Row Address Strobe) I/P: The row address strobe RAS# is an active low command signal issued by DDR3 SDRAM controller to DDR3 SDRAM Memory. It is issued in conjunction with the CAS# and WE signals and is latched at the positive edges of CLK. Different signal levels of RAS, CAS. WE and CS DDR3 SDRAM controller issues different type of commends to DDR3 SDRAM Memory to perform different operations and are referenced to VREFCA.

WE (Write Enable) I/P: The Write Enable signal WE is an active low command signal issued by DDR3 SDRAM controller to DDR3 SDRAM Memory. It is issued in conjunction with RAS and CAS signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command.

BAn (Bank Address) I/P: The Bank Address issued by DDR3 SDRAM controller to DDR3 SDRAM Memory. These signals specify which bank within the DDR3 SDRAM is being accessed.  It define to which bank an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.

RESET# I/P: RESET# input is an active LOW signal & referenced to VSS (ground). The RESET# input receiver is designed as a CMOS input, characterized by a rail-to-rail signal with DC HIGH (logic high) ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. The assertion (activation) and deassertion (deactivation) of the RESET# signal are asynchronous, meaning they occur independently of the clock signal and other commands, providing a reliable mechanism for resetting the DDR3 memory device.

 ZQ[1:0] I/P: In DDR3, the ZQ (Impedance Calibration) signal is associated with output drive calibration. This Pin is connected to an external 240Ω resistor (RZQ), and this resistor is further connected to VSSQ (ground for the output buffer). The purpose of this configuration is to facilitate impedance calibration in the memory module, helping to optimize signal integrity and performance by adjusting the output drive characteristics. The external resistor tied to the ZQ Pins plays a role in determining the impedance values during calibration, enhancing the overall reliability of the DDR3 memory interface.

DDR3/DDR3L Power Supply Signals: 

• VDD Supply (Power supply):
  • DDR3 1.5V ±0.075V.
  • DDR3L Voltage: 1.35V (Operational range: 1.283V to 1.45V)
  • Provides power to the overall device.
• VDDQ Supply (DQ power supply):
  • DDR3 1.5V ±0.075V
  • DDR3L Voltage: 1.35V (Operational range: 1.283V to 1.45V)
  • Supplies power specifically to the data input/output circuits. Isolated on the device for improved noise immunity.
• VREFCA Supply (Reference voltage for control, command, and address):
  • Must be maintained at all times, including self-refresh, for proper device operation.
  • Used as a reference voltage for control, command, and address signals.
• VREFDQ Supply (Reference voltage for data):
  • Must be maintained at all times, including self-refresh, for proper device operation.
  • Serves as a reference voltage for data signals.
• VSS Supply (Ground):
  • Common ground reference for the entire device.
• VSSQ Supply (DQ ground):
  • Isolated ground for the data input/output circuits.
  • Improves noise immunity by providing a separate ground for the data paths.

DDR3 SDRAM Addressing

1Gb: x4, x8, x16 DDR3 SDRAM Addressing:

Parameter	256 Meg x 4	128 Meg x 8	64 Meg x 16
Configuration	32 Meg x 4 x 8 banks	16 Meg x 8 x 8 banks	8 Meg x 16 x 8 banks
Refresh count	8K	8K	8K
Row address	A[13:0] (16K)	A[13:0] (16K)	A[12:0] (8K)
Bank address	BA[2:0] (8)	BA[2:0] (8)	BA[2:0] (8)
Column address	A[11, 9:0] (2K)	A[9:0] (1K)	A[9:0] (1K)

 

Functional Block Diagram:- 256 Meg Locations x 4-Bits Bus

Memory calculations for above memory DDR3 SDRAM organizations:-

Data Bus Width = 4-Bits

No of Row Address Bits: – 14

No of Column Address Bits: – 11

No of Banks = 8

Total number of Memory locations in the DDR3 SDRAM=

2^No of Row Address Bits x 2^ No of Column Address Bits x No of Banks

= 2^14 x 2^ 11 x 8 = 2^14 x 2^ 11 x 2^3 = 2^28 =256 Mega locations

Total Size of DDR3 SDRAM memory =

Data Bus Width x Total number of Memory locations in the DDR3 SDRAM

= 4- bit x 128 Mega locations = 1Gb

Functional Block Diagram:- 128 Meg Locations x 8-Bits Bus

Memory calculations for above memory DDR3 SDRAM organizations:-

Data Bus Width = 8-Bits

No of Row Address Bits: – 14

No of Column Address Bits: – 10

No of Banks = 8

Total number of Memory locations in the DDR3 SDRAM=

2^No of Row Address Bits x 2^ No of Column Address Bits x No of Banks

= 2^14 x 2^ 10 x 8 = 2^14 x 2^ 10 x 2^3 = 2^27 = 128 Mega locations

Total Size of DDR3 SDRAM memory =

Data Bus Width x Total number of Memory locations in the DDR3 SDRAM

= 8-Bits x 618 Mega locations = 1Gb

Functional Block Diagram:- 64 Meg Locations x 16-Bits Bus

Memory calculations for above memory DDR3 SDRAM organizations:-

Data Bus Width = 16-Bits

No of Row Address Bits: – 13

No of Column Address Bits: – 10

No of Banks = 4

Total number of Memory locations in the DDR3 SDRAM=

2^No of Row Address Bits x 2^ No of Column Address Bits x No of Banks

= 2^13 x 2^ 10 x 8 = 2^13 x 2^10 x 2^3 = 2^26 = 64 Mega locations

Total Size of DDR3 SDRAM memory =

Data Bus Width x Total number of Memory locations in the DDR3 SDRAM

= 16-Bits x 64 Mega locations = 1Gb

Summary

In summary, interfacing DDR3 SDRAM involves careful consideration of specifications, proper signal connections, power distribution, and thorough testing for optimal performance. Compliance with standards and documentation of design details are essential for a successful interface.

• Interfacing DDR3 SDRAM
  • Use a DDR3 memory controller adhering to the JESD79-3C standard.
  • Establish a glueless connection for seamless communication.
  • Support features like self-refresh mode, prioritized refresh, customizable parameters (refresh rate, CAS latency).
  • New features include ZQ Calibration and Reset Pin Functionality.
• ODT Functionality
  • Dynamic On-Die Termination (ODT) addresses signal reflection.
  • Incorporates termination resistance in DRAM.
  • Activates termination resistance on data I/O pins, data strobe signals, and write data mask signals.
• DDR3 SDRAM Interface Steps
  • Select a compatible MPU/FPGA/Controller.
  • Understand DDR3 specifications.
  • Connect according to DDR3 SDRAM datasheet.
  • Consider clocking, address, and command signal connections.
  • Pay attention to data bus routing and signal integrity.
  • Ensure stable power and ground.
  • Implement termination and impedance matching.
  • Consider calibration and training algorithms supported by the DDR3 controller.
  • Rigorously test the interface using simulation tools and hardware debuggers.
  • Document design details referring to datasheets for specific guidelines.
• Power and Ground
  • Provide stable power and ground connections to DDR3 SDRAM.
  • Ensure proper power distribution for reliable operation.
• Termination and Impedance Matching
  • Implement termination resistors and impedance matching.
  • Optimize signal integrity, reducing signal reflections.